1. Field of the Invention
The present invention relates to a system and method for designing a semiconductor device. More particularly, the present invention relates to a system and method for designing interconnections for forming a circuit by connecting a large number of elements provided on a semiconductor substrate.
2. Description of the Related Art
A semiconductor device is provided with circuits to achieve desired functions. In order to form the circuits, it is necessary to interconnect a large number of elements such as a transistors formed on a semiconductor substrate with a large number of interconnections. The space between interconnections and the width of each interconnection are not constant and depends on a required operation speed and current capacity, and further depends on a layout of each element formed on the substrate. Supposing that the width of a certain interconnection is W, the width of another interconnection may be “W−w1” (i.e. interconnection with a smaller width) or “W+w2” (i.e. interconnection with a larger width). The same is applied to the interconnection interval. The above-mentioned “w1” and “w2” are expressed by “n times d”. Here, “n” is 0 or a positive integer, while “d” is a change unit of the interconnection width and interconnection interval. In the design and manufacturing of semiconductor devices, a minimum dimension unit in which elements and interconnections are allowed to be laid out through a layout tool, a mask pattern data production, a process restriction, and so on. Therefore, the change unit d of the interconnection width and interconnection interval is equal to the minimum dimension unit. That is, free setting is possible with respect to the widths and spaces of interconnections for connecting elements with the minimum dimension unit as the change unit d.
On the other hand, the semiconductor device is manufactured by using photolithography technique. In such a case, it is known that a shape (a finish shape) actually exposed and processed onto a semiconductor substrate is different from a mask due to the effect of a proximity pattern as patterns are miniaturized. For this reason, a mask is not produced by using an interconnection pattern data as a mask pattern data without any change from the interconnection pattern data, but that a mask pattern but is produced through addition of OPC (Optical Proximity Correction). That is, as shown in FIG. 1, it is supposed that an interconnection pattern data is produced for an interconnection group 520 having an interconnection width W and an interconnection interval P, an interconnection group 510 having the interconnection width W−w1 and the interconnection interval P, and an interconnection group 530 having the interconnection width W+w2 and the interconnection interval P. A mask pattern data is not produced by using only the interconnection pattern data shown in FIG. 1, but the mask is produced by correcting the mask pattern data based on an OPC data 550. In FIG. 1, the correction is not carried out to a mask pattern 521 corresponding to the interconnection group 520, in which the interconnection width W is employed as a width on the mask. On the other hand, in the interconnection groups 510 and 530, the mask patterns 511 and 531 are produced to have “W−m1” and “W+m2”, respectively, as the actual widths on the mask.
In recent years, miniaturization of the semiconductor device is increasingly advanced. Under such conditions, it is difficult to employ the OPC.
This is because the effect of proximity patterns is greater and the extent of the effect is not proportion to the change in the interconnection width and interconnection interval as patterns become miniaturized. For example, the ratio of a difference between a design value and a finish dimension to a correction value of a mask dimension is called as MEEF (Mask Error Enhancement Factor). That is, when MEEF is x, correction of 1 nm on a mask corresponds to a difference of x nm in the finish dimension. While MEEF is approximately 1 when a pattern having the interconnection width of 1000 nm and the interconnection interval of 1000 nm is exposed, MEEF is increased up to approximately 5 when a pattern having the interconnection width of 100 nm and the interconnection interval 100 nm is exposed. This means that the change of 1 nm in the mask dimension leads to the change of 5 nm in the finish dimension. Moreover, it indicates that 5% (=5 nm/100 nm) has to be permitted as a variation in the interconnection width.
As mentioned above, in the conventional semiconductor device, there is a problem that a deviation of the interconnection width and/or the interconnection interval from a design value increases due to the limit of the OPC so that an expected operation and performance cannot be obtained.
Moreover, a large amount of OPC data is used since the minimum dimension unit is used as an increment unit in the interconnection width and interconnection interval. As a result, the number of processes is increased for setting and verification of the OPC data. In addition, the processing system is made large in scale as well as the increase in processing time, since it is necessary to select a given correction data from the large amount of the OPC data and calculate the dimension in a high accuracy. Furthermore, the OPC data needs to be re-checked each time a manufacturing process condition is changed, causing a situation which is difficult to cope with.